ADC 2 Manual do Utilizador descarregar pdf (Página 17)

REV. A

AD7866

–17–

102

THREE-STATE

SCLK

OUT

Figure 17. Entering Partial Power-Down Mode

116

INVALID DATA VALID DATA

SCLK

OUT

THE PART BEGINS

TO POWER UP

THE PART MAY BE FULLY

POWERED UP; SEE POWER-UP

TIMES SECTION

Figure 18. Exiting Partial Power-Down Mode

116

INVALID DATA INVALID DATA

THREE-STATE THREE-STATE

SCLK

OUT

THE PART ENTERS

PARTIAL POWER-DOWN

THE PART BEGINS

TO POWER UP

THE PART ENTERS

FULL POWER-DOWN

Figure 19. Entering Full Power-Down Mode

116

INVALID DATA VALID DATA

SCLK

OUT

THE PART BEGINS

TO POWER UP

THE PART IS

FULLY POWERED UP

POWER UP

Figure 20. Exiting Full Power-Down Mode

Then, to place the AD7866 in normal mode, a dummy cycle

(1 µs to 4 µs approximately) should be initiated. If the first valid

conversion is performed directly after the dummy conversion,

care must be taken to ensure that adequate acquisition time has

been allowed. As mentioned earlier, when powering up from the

power-down mode, the part will return to track upon the first

SCLK edge applied after the falling edge of CS. However when

the ADC initially powers up after supplies are applied, the

track-and-hold will already be in track. This means that (assuming

one has the facility to monitor the ADC supply current and thus

determine which mode the AD7866 is in) if the ADC powers up

in the desired mode of operation and thus a dummy cycle is not

required to change mode, then neither is a dummy cycle required

to place the track-and-hold into track. If no current monitoring

facility is available, the relevant dummy cycle(s) should be

performed to ensure the part is in the required mode.

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