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© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 95
Component
Designator
Value/Type Function PCB Layout Constraints
C13 10uF Power source decoupling
C14 100nF Analogue Power decoupling Adjacent to U1 pin 13
C16
100nF
Digital power decoupling
Adjacent to U1 pin 49
C15
100nF
VB Synth decoupling
Less than 5mm from U1 pin 10
C18
47pF
VB Synth decoupling
Less than 5mm from U1 pin 10
C2
10nF
VB VCO decoupling
Less than 5mm from U1 pin 12
C24
47pF
VB VCO decoupling
Less than 5mm from U1 pin 12
C3 100nF VB RF decoupling Less than 5mm from U1 pin 16 and U1 pin 18
C12 47pF VB RF decoupling Less than 5mm from U1 pin 16 and U1 pin 18
C8
100nF
VB A decoupling
Less than 5mm from U1 pin 27
C9
47pF
VB A decoupling
Less than 5mm from U1 pin 27
C6
100nF
VB RAM decoupling
Less than 5mm from U1 pin 35
C7
100nF
VB Dig decoupling
Less than 5mm from U1 pin 40
R1 43k I Bias Resistor Less than 5mm from U1 pin 14
C20 100nF Vref decoupling Less than 5mm from U1 pin 15
U2
4Mbit
Serial Flash Memory (Numonyx M25P40)
Y1
32MHz
Crystal (AEL X32M000000S025) (CL = 9pF, Max ESR 40R)
C10
15pF +/-5% COG
Crystal Load Capacitor
Adjacent to pin 8 and Y1 pin 1
C11
15pF +/-5% COG
Crystal Load Capacitor
Adjacent to pin 9 and Y1 pin 3
R2
Not fitted
C1 47pF AC Coupling
Phycomp 2238-869-15479
Must be copied directly from the reference design.
L1 5.6nH RF Matching Inductor
MuRata LQP15MN5N6B02
L2 2.7nH Load Inductor
MuRata LQP15MN2N7B02
Table 8: JN5148 Printed Antenna Reference Module Components and PCB Layout Constraints
The paddle should be connected directly to ground. Any pads that requiring connection to ground should do so by
connecting directly to the paddle.
- Data Sheet: JN5148-001 1
- Contents 2
- 20 Analogue Peripherals 58 4
- 1 Introduction 6
- 1.3 Peripherals 7
- 1.4 Block Diagram 8
- 2 Pin Configurations 9
- 2.1 Pin Assignment 10
- 2.2 Pin Descriptions 12
- 2.2.5 Analogue Peripherals 13
- 2.2.6 Digital Input/Output 13
- 4 Memory Organisation 16
- 4.4 External Memory 17
- 4.2 RAM 17
- 4.3 OTP eFuse Memory 17
- 4.5 Peripherals 18
- 4.6 Unused Memory Addresses 18
- 5 System Clocks 19
- 32KXTALOUT 20
- 32KXTALIN 20
- 6 Reset 21
- 6.2 External Reset 22
- 6.3 Software Reset 22
- 6.4 Brown-out Detect 23
- 6.5 Watchdog Timer 23
- 7 Interrupt System 24
- 7.3 Hardware Interrupts 25
- 8 Wireless Transceiver 26
- 8.1.2 Antenna Diversity 27
- ADO (DIO[12]) 28
- TX Active 28
- RX Active 28
- ADE (DIO[13]) 28
- 8.2 Modem 29
- 8.3 Baseband Processor 30
- 8.4 Security Coprocessor 31
- 8.5 Location Awareness 31
- 8.6 Higher Data Rates 32
- 9 Digital Input/Output 33
- Figure 22 DIO Block Diagram 34
- 11 Timers 38
- 11.1.2 Capture Mode 39
- 11.1.3 Counter/Timer Mode 40
- 11.1.4 Delta-Sigma Mode 40
- 11.2 Tick Timer 41
- 11.3 Wakeup Timers 42
- 12 Pulse Counters 44
- 13 Serial Communications 45
- 13.1 Interrupts 46
- 13.2 UART Application 46
- 14 JTAG Debug Interface 47
- 15 Two-Wire Serial Interface 48
- 15.2 Clock Stretching 49
- Right R2 R1 R0 L2 L1 L0Left 52
- R2 R1 R0 L2 L1 L0 52
- 17 Random Number Generator 53
- 18 Sample FIFO 54
- 19.1 Data Transfer Format 55
- 20 Analogue Peripherals 58
- 20.1.1 Operation 59
- 20.1.2 Supply Monitor 60
- 20.1.3 Temperature Sensor 60
- 20.2.1 Operation 60
- 20.3 Comparators 61
- 21.1 Operating Modes 62
- 21.2 Active Processing Mode 62
- 21.3 Sleep Mode 62
- 21.4 Deep Sleep Mode 63
- 22.1 Maximum Ratings 64
- 22.2.2.1 Active Processing 65
- 22.2.2.2 Sleep Mode 65
- 22.2.2.3 Deep Sleep Mode 65
- 22.3 AC Characteristics 66
- Internal RESET 67
- 22.3.2 SPI MasterTiming 68
- 22.3.7 Bandgap Reference 71
- 22.3.10 Comparators 73
- 22.3.11 32kHz RC Oscillator 73
- 22.3.14 24MHz RC Oscillator 75
- 22.3.15 Temperature Sensor 75
- 22.3.16 Radio Transceiver 76
- A.2 PCB Decal 82
- A.3 Ordering Information 83
- JN5148-001 84
- B.1 Crystal Oscillators 88
- B.2 32MHz Oscillator 90
- 32MHz Crystal Oscillator 91
- B.3 32kHz Oscillator 92
- Normalised Current (IDD) 93
- B.4.1 Schematic Diagram 94
- Related Documents 97
- RoHS Compliance 97
- Status Information 97
- Disclaimers 98
- Trademarks 98
- Version Control 99
- Contact Details 100
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