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I / O

GND

TO INTERNAL

CIRCUITRY

ADC12D1800RF

SNAS518I –JULY 2011–REVISED JANUARY 2014

www.ti.com

Operating Ratings

(1)(2)

(continued)

+/- Power 15.3 dBm (maintaining common mode voltage, a.c.-coupled)

17.1 dBm (not maintaining common mode voltage, a.c.-coupled)

Ground Difference

max(GND

TC/DR/E

) -min(GND

TC/DR/E

) 0V

CLK+/- Voltage Range 0V to V

Differential CLK Amplitude 0.4V

P-P

to 2.0V

P-P

Common Mode Input Voltage V

CMO

- 150mV < V

CMI

< V

CMO

+150mV

3.3 Package Thermal Resistance

(1)

Package θ

JC1

JC2

292-Ball BGA Thermally Enhanced Package 16°C/W 2.9°C/W 2.5°C/W

(1) Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.

3.4 Converter Electrical Characteristics

Static Converter Characteristics

Unless otherwise specified, the following apply after calibration for V

= V

= +1.9V; I- and Q-channels, AC-

coupled, unused channel terminated to AC ground, FSR Pin = High; C

= 10 pF; Differential, AC coupled Sine Wave

Sampling Clock, f

CLK

= 1.8 GHz at 0.5 V

P-P

with 50% duty cycle (as specified); V

= Floating; Extended Control Mode with

Demultiplex Non-DES Mode; Duty Cycle Stabilizer on. Boldface limits apply for T

= T

MIN

to T

MAX

and for T

< 105°C. All

other limits T

= 25°C, unless otherwise noted.

(1)(2)(3)

ADC12D1800RF

Units

Symbol Parameter Conditions

(Limits)

Typ Lim

Resolution with No Missing Codes 12 bits

INL Integral Non-Linearity 1 MHz DC-coupled over-ranged

±2.5 LSB

(Best fit) sine wave

DNL Differential Non-Linearity 1 MHz DC-coupled over-ranged

±0.4 LSB

sine wave

OFF

Offset Error 5 LSB

OFF

_ADJ Input Offset Adjustment Range Extended Control Mode ±45 mV

PFSE Positive Full-Scale Error See

(4)

±25 mV (max)

NFSE Negative Full-Scale Error See

(4)

±25 mV (max)

Out-of-Range Output Code

(5)

+) − (V

−) > + Full Scale 4095

+) − (V

−) < − Full Scale 0

(1) The analog inputs, labeled "I/O", are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may

damage this device.

(2) To ensure accuracy, it is required that V

, V

and V

be well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) Typical figures are at T

= 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing

Quality Level).

(4) Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for

this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 4-2. For relationship between Gain

Error and Full-Scale Error, see Specification Definitions for Gain Error.

(5) This parameter is specified by design and is not tested in production.

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