ADC 2 Especificações descarregar pdf (Página 15)

f =

-3dB

ln(2) (n+1)´

2 tp ´

ACQ

ADS7865

www.ti.com

SBAS441C –OCTOBER 2008–REVISED APRIL 2012

Analog-to-Digital Converter (ADC)

The minimum –3dB bandwidth of the driving

operational amplifier can be calculated as shown in

The ADS7865 includes two SAR-type, 2MSPS, 12-bit

Equation 1, with n = 12 being the resolution of the

ADCs (shown in the Functional Block Diagram on the

ADS7865:

front page of this data sheet).

CONVST

(1)

The analog inputs are held with the falling edge of the

With t

ACQ

= 62.5ns, the minimum bandwidth of the

CONVST (conversion start) signal. The setup time of

driving amplifier is 23MHz. The required bandwidth

CONVST referred to the next rising edge of CLOCK

can be lower if the application allows a longer

(system clock) is 10ns (minimum). The conversion

acquisition time.

automatically starts with the rising CLOCK edge.

CONVST should not be issued during a conversion,

A gain error occurs if a given application does not

that is, when BUSY is high.

fulfill the settling requirement shown in Equation 1. As

a result of pre-charging the capacitors, linearity and

CLOCK

THD are not directly affected, however.

The ADC uses an external clock in the range of

The OPA365 from Texas Instruments is

1MHz to 32MHz. 12 clock cycles are needed for a

recommended as a driver; in addition to offering the

complete conversion; the following clock cycle is used

required bandwidth, it provides a low offset and also

for pre-charging the sample capacitors and a

offers excellent THD performance.

minimum of two clock cycles are required for the

The phase margin of the driving operational amplifier

sampling. With a minimum of 16 clocks used for the

is usually reduced by the ADC sampling capacitor. A

entire process, one clock cycle is left for the required

resistor placed between the capacitor and the

setup and hold times along with some margin for

amplifier limits this effect; therefore, an internal 200Ω

delay caused by layout. The clock input can remain

resistor (R

SER

) is placed in series with the switch. The

low between conversions (after applying the 16th

switch resistance (R

) is typically 50Ω (see the

falling edge to complete a running conversion). It can

Equivalent Input Circuit ).

also remain low after applying the 14th falling edge

during a DAC register write access if the device is not

The differential input voltage range of the ADC is

required to perform a conversion (for example, during

±V

REF

, the voltage at the REF

pin.

an initiation phase after power-up).

It is important to keep the voltage to all inputs within

The CLOCK duty cycle should be 50%. However, the

the 0.1V limit below AGND and above AV

while not

ADS7865 functions properly with a duty cycle

allowing dc current to flow through the inputs. Current

between 30% and 70%.

is only necessary to recharge the sample-and-hold

capacitors.

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 32 33

Comentários a estes Manuais

Sem comentários

ADC 2 Especificações Página 15

Comentários a estes Manuais

Manuais e produtos relacionados com Redes ADC 2