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LTC4261/LTC4261-2

42612fd

For more information www.linear.com/LTC4261

master acknowledges the transmitted data byte, as in a

Read Word command, the LTC4261/LTC4261-2 will re-

peat the requested register as the second data byte. Note

that the Register Address pointer is not cleared at the

end of the transaction. Thus the Receive Byte protocol

can be used to repeatedly read a speciﬁc register

Alert Response Protocol

The L

TC4261/LTC4261-2 implement the SMBus Alert

Response Protocol as shown in Figure 16. If enabled

to do so through the ALERT register C, the LTC4261/

LTC4261-2 will respond to faults by pulling the ALERT

pin low. Multiple LTC4261/LTC4261-2s can share a com

mon ALERT line and the protocol allows a master to de-

termine which L

TC4261/LTC4261-2s are pulling the line

low. The master begins by sending a ST

ART bit followed

by the special Alert Response Address (0001 100)b with

the R/W bit set to one. Any LTC4261/LTC4261-2 that is

pulling its ALERT pin low will acknowledge and begin

sending back its individual slave address.

Figure 16. LTC4261 Serial Bus SDA Alert Response Protocol

APPLICATIONS INFORMATION

this means repeated or continuing faults will not gener-

ate alerts until the associated FAULT register bit has been

cleared.

Single-Wire Broadcast Mode

The L

TC4261/LTC4261-2 provides a single-wire broadcast

mode in which selected register data are sent out to the

SDAO pin without clocking the SCL line (Figure 17). The

single-wire broadcast mode is enabled by setting the

ADR1 pin high and the ADR0 pin low (the I

C interface is

disabled). At the end of each conversion of the three ADC

channels, a stream of eighteen bits are broadcasted to

SDAO with a serial data rate of 15.3kHz ±20% in a format

as illustrated in Figure 18. The data bits are encoded with

an internal clock in a way similar to Manchester encoding

that can be easily decoded by a microcontroller or FPGA.

Each data bit consists of a noninverting phase and an

inverting phase. During the conversion of each ADC chan

nel, SDAO is idle at high. At the end of the conversion, the

SDAO pulls low. The START bit indicates the beginning of

data broadcasting and is used along with the dummy bit

(DMY) to measure the internal clock cycle (i.e., the serial

data rate). Following the DMY bit are two channel code

bits CH1 and CH0 labeling the ADC channel (see Table

10). Ten data bits of the ADC channel (ADC9-0) and three

FAULT register bits (B2, B1 and B0) are then sent out. A

parity bit (PRTY) ends each data stream. After that the

SDAO line enters the idle mode with SDAO pulled high.

The following data reception procedure is recommended:

0. Wait for INTV

rising edge.

1. Wait for SDAO falling edge.

2. The first falling edge could be a glitch, so check again

after a delay of 10µs. If back to high, wait again. If still

low, it is the START bit.

3. Use the following low-to-high and high-to-low transis

tions to measure 1/2 of the internal clock cycle.

ALERT

RESPONSE

ADDRESS

0 0 0 1 1 0 0

DEVICE

ADDRESS

0 0 1 a3:a0 0 11

42612 F16

A A

An arbitration scheme ensures that the LTC4261/

LTC4261-2 with the lowest address will have priority;

all others will abort their response. The successful re

sponder will then release its ALERT pin while any others

will continue to hold their ALERT pins low. Polling may

also be used to search for any LTC4261/LTC4261-2 that

have detected faults. Any LTC4261/LTC4261-2 pulling its

ALERT pin low will also release it if it is individually ad

dressed during a read or write transaction.

The ALER

signal will not be pulled low again until the

FAULT register indicates a different fault has occurred or

the original fault is cleared and it occurs again. Note that

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