ADC 2 Especificações descarregar pdf (Página 27)

LTC4261/LTC4261-2

42612fd

For more information www.linear.com/LTC4261

Figure 17. Single-Wire Broadcast Mode

Figure 18. Single-Wire Broadcast Data Format

4. Wait for the second low-to-high transistion (middle of

DMY bit).

5. Wait 3/4 of a clock cycle.

6. Sample bit CH1, wait for transistion.

7. Wait 3/4 of a clock cycle.

8. Sample bit CH0, wait for transistion.

9. Wait 3/4 of a clock cycle.

10. Sample ADC9, wait for transistion.

11. Continue until all bits are read.

APPLICATIONS INFORMATION

The above procedure can be ported to a microcontroller

or used to design a state machine in FPGA. Code should

have timeouts in case an edge is missed. Abort the read

if it takes more than double the typical time (1.2ms) for

all 18 bits to be clocked out.

A typical application circuit with the LTC4261/LTC4261-2

in the broadcast mode is illustrated in Figure 19, where

input voltage, V

of the FET and V

SENSE

are monitored.

The register addresses and contents are summerized in

Table 1 and Table 2. The function of each register bit is

detailed in Tables 3 to 9.

SDAI

SCL

SDAO

ADR1

ADR0

LTC4261

INTV

6 × 0.51k IN SERIES

1/4W EACH

–48V RTN

–48V INPUT

0.1µF

1µF

7.5k

42612 F17

GND

ANODE

CATHODE

HCPL-0300

OUT

MICRO-

CONTROLLER

INTERNAL

CLK

DATA

SDAO

START

START DMY CH1 CH0 OC OV PRTY

4261 F18

UVADC9

.. .. ..

ADC0

CH1

CH0

ADC9

ADC0

ADC9

ADC0

PRTY

1 2 ... 22 23 24 25 26 27 28 29 30 31 32 33 34

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