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TLC2543 to H8/325 Microcontroller Interface

Microcontroller Features

The individual members of the H8 family of microcontrollers can be differentiated by various criteria, for example the

inclusion or otherwise of an on-board 8-bit resolution analog-to-digital converter (ADC). Those members which include

an ADC generally cost between 10 and 20 percent more than their counterparts which do not.

System requirements such as ADC resolution, remote location of ADC, flexibility, and total cost all influence the final

choice of microcontroller architecture. The H8/325, used for this application report, does not include an on-board ADC

but provides 1K of RAM, 32K of ROM, and two serial I/O ports. It is therefore well suited to interfacing with the

TLC2543 serial output ADC.

Interface Circuit

Figure 11 illustrates a typical 12-bit data acquisition system which uses the H8/325 microcontroller to coordinate the

operation of the TLC2543 ADC via one of its serial (SCI) ports. The circuit uses the H8’s 8-bit parallel I/O port 4 to

route ADC channel and mode information into the microcontroller. This information could be provided by a host system

data bus or, as in Figure 6, by a bank of eight manually operated toggle switches situated on the same printed circuit board

as the microcontroller.

NOTE: Single Chip Mode (MD0 = MD1 = 1)

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

I/O CLOCK

DATA INPUT

DATA OUT

TLC2543 H8/325

SCK0/P5.2

TxD0/P5.0

RxD0/P5.1

P6.0

MD0

MD1

XTAL

EXTAL

GND

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

20 MHz

(max)

ADC Mode

Channel

Number

5 V

Analog

Inputs

Figure 11. TLC2543 to H8/300 Microcontroller Interface Circuit

Software

List 2 shows the program which was written to coordinate the interface. It uses three subroutines to implement the overall

interface to the TLC2543. The first of these is called DATAIN which reads ADC channel and mode information into

the microcontroller. It also maps converter channel numbers to corresponding addresses in RAM where conversion

results can be stored. In this case the addresses from 0040H to 0067H were chosen to store the results. The most

significant byte of each result is placed in an even address and the least significant byte of each result is placed in the

corresponding adjacent odd address.

The conversion result of each channel is stored in left justified format and therefore occupies the upper 12 bits of the

16-bit words which occupy even addresses from 0040H up to 0066H.

The second subroutine to be used is ADC. This begins by producing a chip-select high pulse. The trailing negative edge

of this pulse is rapidly followed by the transmission of channel and mode information to the converter.

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