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TLC2543 to 80C51 Microcontroller Interface

Microcontroller Features

The 80C51 microcontroller family does not provide an SPI or equivalent facility. In order to implement the interface

with the TLC2543 analog-to-digital converter, it is necessry to use software to synthesize the operation of an SPI. This

results in a slower data transfer rate which is governed by the microcontroller’s instruction cycle times. These are, in

turn, influenced by the clock frequency of the microcontroller. The highest clock frequency possible should therefore

be selected for the microcontroller to minimize instruction cycle times and thus optimize the data transfer rate of the

interface.

Interface Circuit

Figure 13 shows the circuit for the interface of the TLC2543 to the 80C51 microcontroller. The I/O CLOCK, DATA

INPUT and CS inputs to the TLC2543 are provided via the bidirectional parallel port 1 terminals P1.0, P1.1, and P1.3

respectively. Conversion result data from the TLC2543 is received by the 80C51 through the P1.2 terminal of port 1.

The channel select/mode data is input to the microcontroller via port 3.

I/O CLOCK

DATA INPUT

DATA OUT

TLC2543 80C51

P1.0

P1.1

P1.2

P1.3

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

ADC Mode

Channel

Number

5 V

GND

Figure 13. TLC2543 to 80C51 Microcontroller Interface

Software

The listing for the program used to control the interface circuit mentioned above is shown in List 4. As for the other

microcontroller interface programs, it consists of a main program and two subroutines – TLC2543 and STORE.

The main program initializes the directions of the port 1 I/O terminals. P1.2 is configured as an input. P1.0, P1.1, and

P1.3 are all programmed to perform as outputs. The chip select terminal of the TLC2543 is set high by setting P1.3.

TLC2543 is then called. This subroutine contains the instructions which synthesize the SPI function and controls the

exchange of data between the microcontroller and the TLC2543. The least significant bit first (LSBF) flag which is bit

1 of the channel select/mode data byte is checked to determine which byte (most significant – MSByte, least significant

– LSByte) of the conversion result is to be expected first.

The SPI function is synthesized by using the accumulator in conjunction with the rotate left through carry (RLC)

instruction to act as the SPI shift register. The following sequence provides a slow motion version of the SPI function.

The first bit of the first byte of the conversion result is read into the carry (C) bit. The contents of the accumulator are

rotated left through carry and the first bit of the channel select/mode data is then output from P1.1. The first pulse of

the serial clock is then provided by toggling the P1.0 bit of port 1 first high and then low. This sequence is repeated seven

more times to complete the transfer of the first byte of data.

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