ADC 320F Especificações descarregar pdf (Página 18)

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Autoconversion Sequencer Principle of Operation

Example 1-1. Simultaneous Sampling Dual Sequencer Mode Example

Example initialization:

AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x1; // Setup simultaneous sampling mode

AdcRegs.ADCMAXCONV.all = 0x0033; // 4 double conv's each sequencer (8 total)

AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup conv from ADCINA0 & ADCINB0

AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup conv from ADCINA1 & ADCINB1

AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Setup conv from ADCINA2 & ADCINB2

AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Setup conv from ADCINA3 & ADCINB3

AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x4; // Setup conv from ADCINA4 & ADCINB4

AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x5; // Setup conv from ADCINA5 & ADCINB5

AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0x6; // Setup conv from ADCINA6 & ADCINB6

AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0x7; // Setup conv from ADCINA7 & ADCINB7

If SEQ1 and SEQ2 were both executed, the results would go to the following RESULT registers:

ADCINA0 -> ADCRESULT0

ADCINB0 -> ADCRESULT1

ADCINA1 -> ADCRESULT2

ADCINB1 -> ADCRESULT3

ADCINA2 -> ADCRESULT4

ADCINB2 -> ADCRESULT5

ADCINA3 -> ADCRESULT6

ADCINB3 -> ADCRESULT7

ADCINA4 -> ADCRESULT8

ADCINB4 -> ADCRESULT9

ADCINA5 -> ADCRESULT10

ADCINB5 -> ADCRESULT11

ADCINA6 -> ADCRESULT12

ADCINB6 -> ADCRESULT13

ADCINA7 -> ADCRESULT14

ADCINB7 -> ADCRESULT15

18 Analog-to-Digital Converter (ADC) SPRU812A – September 2007 – Revised October 2007

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