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ADC Control Registers

Table 2-1. ADC Control Register 1 (ADCTRL1) Field Descriptions (continued)

Bit(s) Name Value Description

0 Start-stop mode. Sequencer stops after reaching EOS. On the next SOC, the sequencer

starts from the state where it ended unless a sequencer reset is performed.

1 Continuous conversion mode. After reaching EOS, the behavior of the sequencer

depends on the state of the SEQ_OVRD bit. If this bit is cleared, the sequencer starts

over again from its reset state (CONV00 for SEQ1 and cascaded, CONV08 for SEQ2). If

SEQ_OVRD is set, the sequencer starts again from its current position, without

resetting.

5 SEQ_OVRD Sequencer override. Provides additional sequencer flexibility in continuous run mode by

overriding the wrapping around at the end of conversions set by MAX_CONVn.

0 Disabled - Allows the sequencer to wrap around at the end of conversions set by

MAX_CONVn.

1 Enabled - Overrides the sequencer from wrapping around at the end of conversions set

by MAX_CONVn. Wraparound occurs only at the end of the sequencer.

4 SEQ_CASC Cascaded sequencer operation. This bit determines whether SEQ1 and SEQ2 operate

as two 8-state sequencers or as a single 16-state sequencer (SEQ).

0 Dual-sequencer mode. SEQ1 and SEQ2 operate as two 8-state sequencers.

1 Cascaded mode. SEQ1 and SEQ2 operate as a single 16-state sequencer (SEQ).

3-0 Reserved Reads return zero. Writes have no effect.

Figure 2-2. ADC Control Register 2 (ADCTRL2) (Address Offset 01h)

15 14 13 12 11 10 9 8

ePWM_SOCB_SEQ RST_SEQ1 SOC_SEQ1 Reserved INT_ENA_SEQ1 INT_MOD_SEQ1 Reserved ePWM_SOCA_SEQ1

R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R-0 R/W-0

7 6 5 4 3 2 1 0

EXT_SOC_SEQ1 RST_SEQ2 SOC_SEQ2 Reserved INT_ENA_SEQ2 INT_MOD_SEQ2 Reserved ePWM_SOCB_SEQ2

R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; W = Write access, S = Set only, C = Clear - n = value after reset

Table 2-2. ADC Control Register 2 (ADCTRL2) Field Descriptions

Bit(s) Name Value Description

15 ePWM_SOCB_SEQ ePWM SOCB enable for cascaded sequencer (Note: This bit is active only in cascaded

mode.)

0 No action

1 Setting this bit allows the cascaded sequencer to be started by an ePWM SOCB signal.

The ePWM modules can be programmed to start a conversion on various events. See the

TMS320x28xx , 28xxx Enhanced Pulse Width Modulation Module Reference Guide

(literature number SPRU791) for more information on the ePWM modules.

14 RST_SEQ1 Reset sequencer1 Writing a 1 to this bit resets SEQ1 or the cascaded sequencer

immediately to an initial "pretriggered" state, i.e., waiting for a trigger at CONV00. A

currently active conversion sequence will be aborted.

0 No action

1 Immediately reset sequencer to state CONV00

SPRU812A – September 2007 – Revised October 2007 ADC Registers 35

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