ADC 320F Especificações descarregar pdf (Página 40)

www.ti.com

2.3 Autosequence Status Register (ADCASEQSR)

Autosequence Status Register (ADCASEQSR)

Figure 2-5. Autosequence Status Register (ADCASEQSR) (Address Offset 07h)

15 12 11 8

Reserved SEQ_CNTR

R-0 R-0

7 6 4 3 0

Reserved SEQ2_STATE SEQ1_STATE

R-0 R-0 R-0

LEGEND: R/W = Read/Write; R =Read only; x = undefined, - n = value after reset

Table 2-6. Autosequence Status Register (ADCASEQSR) Field Descriptions

Bit(s) Name Description

15-12 Reserved Reads return a zero. Writes have no effect.

11-8 SEQ_CNTR[3:0] Sequencing counter status bits. The SEQ_CNTRn 4-bit status field is used by SEQ1, SEQ2, and

the cascaded sequencer. SEQ2 is irrelevant in cascaded mode. The Sequencer Counter bit field,

SEQ_CNTR[3:0], is initialized to the value in MAX_CONV at the start of a conversion sequence.

After each conversion (or a pair of conversions in simultaneous sampling mode) in an auto

conversion sequence, the Sequencer Counter decreases by 1.The SEQ_CNTR bits can be read at

any time during the countdown process to check status of the sequencer. This value, together with

the SEQ1 and SEQ2 busy bits, uniquely identifies the progress or state of the active sequencer at

any point in time. See Table 2-7 .

7 Reserved Reads return a zero. Writes have no effect.

6-0 SEQ2_STATE[2:0] SEQ2_STATE and SEQ1_STATE bit fields are the pointers of SEQ2 and SEQ1, respectively.

and

SEQ1_STATE[3:0]

Table 2-7. State of Active Sequencer

Number of conversions

SEQ_CNTR (read only) remaining

0000 1 or 0, depending on the busy bit

0001 2

0010 3

0011 4

0100 5

0101 6

0110 7

0111 8

1000 9

1001 10

1010 11

1011 12

1100 13

1101 14

1110 15

1111 16

40 ADC Registers SPRU812A – September 2007 – Revised October 2007

Submit Documentation Feedback

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 46

Comentários a estes Manuais

Sem comentários

ADC 320F Especificações Página 40

Comentários a estes Manuais

Manuais e produtos relacionados com Redes ADC 320F