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2.8 ADC Conversion Result Buffer Registers (ADCRESULTn)

ADC Conversion Result Buffer Registers (ADCRESULTn)

Table 2-11. CONVnn Bit Values and the ADC Input

Channels Selected (continued)

CONVnn Value ADC Input Channel Selected

1101 ADCINB5

1110 ADCINB6

1111 ADCINB7

In the cascaded sequencer mode, registers ADCRESULT8 through ADCRESULT15 holds the results of

the ninth through sixteenth conversions. The ADCRESULTn registers are left justified when read from

Peripheral Frame 2 (0x7108-0x7117) with two wait states and right justified when read from Peripheral

Frame 0 (0x0B00-0x0B0F) with zero wait states.

Figure 2-13. ADC Conversion Result Buffer Registers (ADCRESULTn) - (Addresses 0x7108-0x7117)

15 14 13 12 11 10 9 8

D11 D10 D9 D8 D7 D6 D5 D4

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

7 6 5 4 3 0

D3 D2 D1 D0 Reserved

R-0 R-0 R-0 R-0 R-0

LEGEND: R/W = Read/Write; R = Read only; - n = value after reset

Figure 2-14. ADC Conversion Result Buffer Registers (ADCRESULTn) - (Addresses

0x0B00-0x0B0F)

15 12 11 10 9 8

Reserved D11 D10 D9 D8

R-0 R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

LEGEND: R/W = Read/Write; R = Read only; - n = value after reset

SPRU812A – September 2007 – Revised October 2007 ADC Registers 45

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