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2.1 ADC Control Registers

ADC Control Registers

Figure 2-1. ADC Control Register 1 (ADCTRL1) (Address Offset 00h)

15 14 13 12 11 8

Reserved RESET SUSMOD ACQ_PS

R-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 0

CPS CONT_RUN SEQ_OVRD SEQ_CASC Reserved

R/W-0 R/W-0 R/W-0 R/W-0 R-0

LEGEND: R/W = Read/Write; R = Read only; - n = value after reset

Table 2-1. ADC Control Register 1 (ADCTRL1) Field Descriptions

Bit(s) Name Value Description

15 Reserved Reads return a zero. Writes have no effect.

14 RESET ADC module software reset. This bit causes a master reset on the entire ADC module.

All register bits and sequencer state machines are reset to the initial state as occurs

when the device reset pin is pulled low (or after a power-on reset). This is a

one-time-effect bit, meaning this bit is self-cleared immediately after it is set to 1. Read

of this bit always returns a 0. Also, the reset of ADC has a latency of two clock cycles

(that is, other ADC control register bits should not be modified until two ADC clock

cycles after the instruction that resets the ADC.

0 No effect

1 Resets entire ADC module (bit is then set back to 0 by ADC logic)

Note: The ADC module is reset during a system reset. If an ADC module reset is

desired at any other time, you can do so by writing a 1 to this bit. After two ADC clock

domain cycles, you can then write the appropriate values to the ADCCTRL1 register bits.

The example below assumes 150-MHz DSP Clock and 25-MHz ADCCLK. Assembly

code:

MOV ADCTRL1, #01xxxxxxxxxxxxxxb; Resets the ADC (RESET = 1)

RPT #10|| NOP; Provides the required delay between writes to ADCTRL1

MOV ADCTRL1, #00xxxxxxxxxxxxxxb ; Configures ADCTRL1 to user-desired value.

Note that the second MOV is not required if the default configuration is sufficient.

13-12 SUSMOD[1:0] Emulation-suspend mode. These bits determine what occurs when an

emulation-suspend occurs (due to the debugger hitting a breakpoint, for example).

00 Mode 0. Emulation suspend is ignored.

01 Mode 1. Sequencer and other wrapper logic stops after current sequence is complete,

final result is latched, and state machine is updated.

10 Mode 2. Sequencer and other wrapper logic stops after current conversion is complete,

result is latched, and state machine is updated.

11 Mode 3. Sequencer and other wrapper logic stops immediately on emulation suspend.

11-8 ACQ_PS[3:0] Acquisition window size. This bit field controls the width of SOC pulse, which, in turn,

determines for what time duration the sampling switch is closed. The width of SOC pulse

is ADCTRL1[11:8] + 1 times the ADCLK period.

7 CPS Core clock prescaler. The prescaler is applied to divided device peripheral clock,

HSPCLK.

0 ADCCLK = F

clk

1 ADCCLK = F

clk

Note: F

clk

= Prescaled HSPCLK (ADCCLKPS[3:0])

6 CONT_RUN Continuous run. This bit determines whether the sequencer operates in continuous

conversion mode or start-stop mode. This bit can be written while a current conversion

sequence is active. This bit will take effect at the end of the current conversion

sequence; i.e., software can set/clear this bit until EOS has occurred, for valid action to

be taken. In the continuous conversion mode, there is no need to reset the sequencer;

however, the sequencer must be reset in the start-stop mode to put the converter in

state CONV00.

34 ADC Registers SPRU812A – September 2007 – Revised October 2007

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