ADC 320F Especificações descarregar pdf (Página 26)

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1.4 ADC Clock Prescaler

4-bit clock

divider

(x1, 1/2, ... 1/30)

HSPCLK

ADCTRL3[4-1]

(ADCLKPS[3-0])

x1/2

ADCTRL1[7]=1

(CPS=1)

ADCTRL1[7]=0

(CPS=0)

SOC pulse

generator

S/H clock

pulse

ADCCLK

ADCTRL1[11-8]

(ACQ_PS[3-0])

1.4.1 ADC-module Clock and Sample Rate

PLL

XCLKIN

SH clock/

pulse

No PLL

HISPCP

HSPCLK

ADCLKPS

CPS ADCCLK

ACQ_PS

ADCENCLK

PCLKCR[3]

clk

1.5 Low-power Modes

ADC Clock Prescaler

The peripheral clock HSPCLK is divided down by the ADCCLKPS[3:0] bits of the ADCTRL3 register. An

extra divide-by-two is provided via the CPS bit of the ADCTRL1 register. In addition, the ADC can be

tailored to accommodate variations in source impedances by widening the sampling/acquisition period.

This is controlled by the ACQ_PS[3:0] bits in the ADCTRL1 register. These bits do not affect the

conversion portion of the S/H and conversion process, but do extend the length of time in which the

sampling portion takes by extending the start of the conversion pulse. See Figure 1-9 .

Figure 1-9. ADC Core Clock and Sample-and-Hold (S/H) Clock

A See register bit definition for clock divider ratio and S/H pulse control. S/H pulse width determines the size of

acquisition window (the time period for which sampling switch is closed).

The ADC module has several prescaler stages to generate any desired ADC operating clock speed.

Figure 1-10 defines the clock selection stages that feed the ADC module. Table 1-7 gives two example

settings and shows both the effective sustained sequential sampling rate and the sample and hold window

time for those settings.

Figure 1-10. Clock Chain to the ADC

Table 1-7. Clock Chain to the ADC

XCLKIN SYSCLKOUT HISPCLK ADCTRL3[4-1] ADCTRL1[7] ADCCLK ADCTRL1[11-8] SH Width

HSPCP = 3 ADCLKPS = 0 CPS=0 ACQ_PS = 0

1 ADC Clock

150 MHz/ 25 MHz 25 MHz 12.5 MHz

30 MHz 150 MHz 25 MHz

40 ns

2 X 3 = 25 MHz 12.5 MSPS sustained

conversion rate

HSPCP = 2 ADCLKPS = 2 CPS = 1 ACQ_PS = 15

16 ADC

100 MHz/ 25/2 X 2 = 6.25 MHz/ 183.824 kHz

20 MHz 100 MHz 3.125 MHz Clocks

2 X 2 = 25 MHz 6.25 MHz 2 X 1 = 3.125 183.824 kSPS sustained

5.12 µs

MHz conversion rate

The ADC supports three separate power sources each controlled by independent bits in the ADCTRL3

ADC off.

Analog-to-Digital Converter (ADC)26 SPRU812A – September 2007 – Revised October 2007

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