ADC 320F Especificações descarregar pdf (Página 36)

www.ti.com

ADC Control Registers

Table 2-2. ADC Control Register 2 (ADCTRL2) Field Descriptions (continued)

Bit(s) Name Value Description

13 SOC_SEQ1 Start-of-conversion (SOC) trigger for Sequencer 1 (SEQ1) or the cascaded sequencer.

This bit can be set by the following triggers:

• S/W - Software writing a 1 to this bit

• ePWM SOCA

• ePWM SOCB (only in cascaded mode)

• EXT - External pin (i.e., GPIO Port A pin (GPIO31-0) configured as XINT2 in the

GPIOxINT2SEL register.

See the TMS320x2833x System Control and Interrupts Reference Guide (literature

number SPRUFB0) for details on how to configure a GPIO pin as XINT2. When a trigger

occurs, there are three possibilities:

Case 1: SEQ1 idle and SOC bit clear SEQ1 starts immediately (under arbiter control).

This bit is set and cleared, allowing for any "pending" trigger requests.

Case 2: SEQ1 busy and SOC bit clear Bit is set signifying a trigger request is pending.

When SEQ1 finally starts after completing current conversion, this bit is cleared.

Case 3: SEQ1 busy and SOC bit set Any trigger occurring in this case is ignored (lost).

0 Clears a pending SOC trigger.

Note: If the sequencer has already started, this bit is automatically cleared, and hence,

writing a zero has no effect; i.e., an already started sequencer cannot be stopped by

clearing this bit.

1 Software trigger - Start SEQ1 from currently stopped position (i.e., Idle mode)

Note: The RST_SEQ1 (ADCTRL2.14) and the SOC_SEQ1 (ADCTRL2.13) bits should not

be set in the same instruction. This resets the sequencer, but does not start the

sequence. The correct sequence of operation is to set the RST_SEQ1 bit first, and the

SOC_SEQ1 bit in the following instruction. This makes certain that the sequencer is reset

and a new sequence started. This sequence applies to the RST_SEQ2 (ADCTRL2.6) and

SOC_SEQ2 (ADCTRL2.5) bits also.

12 Reserved Reads return a zero. Writes have no effect.

11 INT_ENA_SEQ1 SEQ1 interrupt enable. This bit enables the interrupt request to CPU by INT SEQ1.

0 Interrupt request by INT_SEQ1 is disabled.

1 Interrupt request by INT_SEQ1 is enabled.

10 INT_MOD_SEQ1 SEQ1 interrupt mode. This bit selects SEQ1 interrupt mode. It affects the setting of INT

SEQ1 at the end of the SEQ1 conversion sequence.

0 INT_SEQ1 is set at the end of every SEQ1 sequence.

1 INT_SEQ1 is set at the end of every other SEQ1 sequence.

9 Reserved Reads return a zero. Writes have no effect.

8 ePWM_SOCA_SEQ1 ePWM SOCA enable bit for SEQ1

0 SEQ1 cannot be started by ePWMx SOCA trigger.

1 Allows SEQ1/SEQ to be started by ePWMx SOCA trigger. The ePWMs can be

programmed to start a conversion on various events.

7 EXT_SOC_SEQ1 External signal start-of-conversion bit for SEQ1

0 No action

1 Setting this bit enables an ADC autoconversion sequence to be started by a signal from a

GPIO Port A pin (GPIO31-0) configured as XINT2 in the GPIOXINT2SEL register. See

the TMS320x2833x System Control and Interrupts Reference Guide (literature number

SPRUFB0)

6 RST_SEQ2 Reset SEQ2

0 No action

1 Immediately resets SEQ2 to an initial "pretriggered" state, i.e., waiting for a trigger at

CONV08. A currently active conversion sequence will be aborted.

36 ADC Registers SPRU812A – September 2007 – Revised October 2007

Submit Documentation Feedback

1 2 ... 31 32 33 34 35 36 37 38 39 40 41 ... 45 46

Comentários a estes Manuais

Sem comentários

ADC 320F Especificações Página 36

Comentários a estes Manuais

Manuais e produtos relacionados com Redes ADC 320F