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Maximum Conversion Channels Register (ADCMAXCONV)

Table 2-4. Maximum Conversion Channels Register (ADCMAXCONV) Field Descriptions

Bit(s) Name Description

15-7 Reserved Reads return a zero. Writes have no effect.

6-0 MAX_CONVn MAX_CONVn bit field defines the maximum number of conversions executed in an autoconversion

session. The bit fields and their operation vary according to the sequencer modes (dual/cascaded).

For SEQ1 operation, bits MAX_CONV1[2:0] are used.

For SEQ2 operation, bits MAX_CONV2[2:0] are used.

For SEQ operation, bits MAX_CONV1[3:0] are used. An autoconversion session always starts with

the initial state and continues sequentially until the end state if allowed. The result buffer is filled in a

sequential order. Any number of conversions between 1 and (MAX_CONVn +1) can be programmed

for a session.

Example 2-1. ADCMAXCONV Register Bit Programming

If only five conversions are required, then MAX_CONVn is set to four.

Case 1: Dual mode SEQ1 and cascaded mode Sequencer goes from CONV00 to CONV04, and the

five conversion results are stored in the registers Result 00 to Result 04 of the Conversion Result

Buffer.

Case 2: Dual mode SEQ2 Sequencer goes from CONV08 to CONV12, and the five conversion results

are stored in the registers Result 08 to Result 12 of the Conversion Result Buffer.

MAX_CONV1 Value >7 for Dual-Sequencer Mode

If a value for MAX_CONV1, which is greater than 7, is chosen for the dual-sequencer mode (i.e., two

separate 8-state sequencers), then SEQ_CNTR will continue counting past seven, causing the

sequencer to wrap around to CONV00 and continue counting.

Table 2-5. Bit Selections for MAX_CONV1 for

Various Number of Conversions

ADCMAXCONV[3-0] Number of Conversions

0000 1

0001 2

0010 3

0011 4

0100 5

0101 6

0110 7

0111 8

1000 9

1001 10

1010 11

1011 12

1100 13

1101 14

1110 15

1111 16

SPRU812A – September 2007 – Revised October 2007 ADC Registers 39

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